Embodiments of the invention relate to a liquid crystal display array substrate and a manufacturing method thereof.
Thin film transistor liquid crystal displays (TFT-LCDs) are an important type of flat panel displays (FPDs).
TFT-LCDs may be classified into a vertical electrical field type and a horizontal electrical field type depending on the direction of the electrical field by which the liquid crystal is driven. For a vertical electrical field type TFT-LCD, a pixel electrode is formed on an array substrate while a common electrode is formed on a color filter substrate. For a horizontal electrical field type TFT-LCD, both a pixel electrode and a common electrode are formed on an array substrate. Therefore, an additional patterning process for forming the common electrode is required when manufacturing a horizontal electrical filed type TFT-LCD array substrate. A vertical electrical field type TFT-LCD comprises a twist nematic (TN) type TFT-LCD. A horizontal electrical field type TFT-LCD comprises a fringe field switching (FFS) type TFT-LCD and an in-plane switching (IPS) type TFT-LCD. Horizontal electrical field type TFT-LCDs, especially FFS type TFT-LCDs, have advantages such as wide view angles and high aperture ratio and have been widely used in practice.
Currently, an FFS type TFT-LCD array substrate is implemented by forming structural patterns via a plurality of patterning processes. Each patterning process comprises processes such as masking, exposing and developing of photoresist, etching and removing remaining photoresist. An etching process comprises dry etching and wet etching. Therefore, the complexity of a method for manufacturing a TFT-LCD array substrate can be evaluated with the numbers of the employed patterning processes, and reducing patterning processes means decreasing manufacturing cost. A six-patterning process for a FFS TFT-LCD array substrate can comprise: patterning for a common electrode, patterning for a gate line and a gate electrode, patterning for an active layer, patterning for source/drain electrodes, patterning for a through hole, and patterning for a pixel electrode.
A conventional four-patterning process for manufacturing a FFS TFT-LCD array substrate comprises the following steps.
Step 1, depositing a first metal film, and forming a gate line, a common electrode line and a gate electrode by a first patterning process with a normal mask.
Step 2, depositing a gate insulating film, an active layer film, and forming an active layer (including stacked layers of a semiconductor layer and a doped semiconductor layer) pattern by a second patterning process with a normal mask.
Step 3, depositing a first transparent conductive film and second metal film sequentially, and forming a pixel electrode, a source electrode, a drain electrode and a TFT channel by a third patterning with a dual tone mask.
Step 4, depositing a passivation layer and a second transparent conductive layer, forming a passivation layer, a connection hole (used for connection between a common electrode and the common electrode line), a connection hole in a PAD region and the common electrode.
The PAD region is a region where leads of a driving circuit board are connected with the array substrate. Through the connection holes in the PAD region, the leads are electrically connected with the gate lines, a data lines, and the common electrode lines on the array substrate.
In the manufacturing method for the array substrate of the liquid crystal display described above, the patterns including the pixel electrode, the source electrode, the drain electrode and the TFT channel are formed merely by one patterning process. However, it has been found that the current manufacturing method may give rise to failure of degrading the display performance of the liquid crystal display, which is described in detail below.
FIG. 1 is a schematic plan view of a conventional FFS type TFT-LCD array substrate. FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1. FIG. 3A is a cross-sectional view after a first transparent conductive layer and a source/drain metal layer are deposited on the substrate with a gate electrode, a gate insulating layer, an active layer formed thereon. FIG. 3B is a cross-sectional view after performing exposure and developing on photoresist on the structure shown in FIG. 3A. FIG. 3C is a cross-sectional view after the etching process is performed. FIG. 3D is a cross-sectional view after performing an ashing process on the photoresist on the structure shown in FIG. 3C. FIG. 3E is a cross-sectional view after etching the substrate shown in FIG. 3D. FIG. 3F is a cross-sectional view showing a state after removing the photoresist shown in FIG. 3E.
As shown in FIG. 1, the conventional FFS type TFT-LCD substrate comprises: a gate line 1, a data line 2, a thin film transistor (TFT) 3, a pixel electrode 4, a common electrode 6 and a common electrode line 5. The gate line 1 is laterally provided on a transparent substrate 11, and the date line 2 is longitudinally provided on the transparent substrate 11, with a TFT 3 formed at an intersection of the gate line 1 and the data line 2. The TFT 3 is an active switching element. The pixel electrode 4 is a plate-shaped electrode, and the common electrode 6 is a slit electrode. The common electrode 6 is located above the pixel electrode 4 with most part of them overlapped, and can form a horizontal electrical field for driving liquid crystal together with the pixel electrode 4. The common electrode line 5 and the common electrode 6 are connected with each other via a connection hole. It should be noted that the reference number “4” in FIG. 1 does not indicate the elongated slit but the plate-shaped pixel electrode under the slit.
As shown in FIG. 2, the conventional FFS type TFT-LCD array substrate further comprises, in particular, the transparent substrate 11, the pixel electrode 4, the common electrode 6, a gate electrode 12, a gate insulating layer 13, an active layer (comprising an semiconductor layer and an doped semiconductor layer) 14, a first transparent conductive portion 15, a source electrode 16, a drain electrode 17, a TFT channel 18 and a passivation layer 19. The gate electrode 12 and the gate line 1 are formed integrally, the source electrode 16 and the date line 2 are formed integrally, and the drain electrode 17 is connected with the pixel electrode 4 directly. When the gate line 1 is input an ON signal, the active layer 14 become conductive, a data signal from the data line 2 can be transferred from the source electrode 16 to drain electrode 17 via the TFT channel, and is further input into the pixel electrode 4. The pixel electrode 4, after input the data signal, generates an electrical field for rotating liquid crystal, together with the common electrode 6. Since the common electrode 6 has slits, it can form a horizontal electrical field with the pixel electrode 4.
The conventional manufacturing method for the FFS type TFT-LCD array substrate is described by referring FIG. 3A-3F. The method comprises the following steps.
Step 1, sequentially depositing a first transparent conductive film 100 and a source/drain metal film 200 on a substrate 11 formed with a gate line, a gate electrode 12, a gate insulating layer 13 and an active layer 14 thereon, as shown in FIG. 3A.
Step 2, applying a layer of photoresist 1000 on the source/drain metal film 200, and performing exposure and development on the photoresist 1000 with a dual tone mask, wherein the thickness of the photoresist 1000 in a pixel region 40 is thinner than that of the photoresist 1000 in a source electrode region 160, a drain electrode region 170 and a data line region, and there is no photoresist 1000 left in other regions including a TFT channel region, as shown in FIG. 3B.
Step 3, performing a first wet etching on the substrate 11 to remove the source/drain metal film 200, the first transparent conductive film 100 and part of the active layer 14 in the region not covered by the photoresist 1000, so as to form a source drain 16 and a TFT channel 18, as shown in FIG. 3C.
Step 4, performing an aching process on the photoresist 1000, which makes the source/drain metal film 200 exposed, and the photoresist 1000 in the source electrode region 160, the drain electrode region 170 and the data line region remained, as shown in 3D.
Step 5, performing a second wet etching on the substrate 11 to remove the source/drain metal film 200 not covered by the photoresist 1000, so as to form a first transparent conductive portion 15, a pixel electrode 4 and a drain electrode 17, as shown in FIG. 3E.
Step 6, removing the remaining photoresist 1000, as shown in FIG. 3F.
In the above-mentioned Steps 3 and 5, etching performed in a large area for the whole substrate are needed to be performed for two times in order to form the TFT channel, the source electrode, the drain electrode and the pixel electrode. This kind of etching in a large area can only be performed by wet etching, that is to say, the substrate is immersed in an etchant solution, and the portion that is not covered by the photoresist and can be contacted by the etchant is etched. In the above mentioned method, the TFT channel region 180 is wet-etched for two times, i.e., one time in Step 3 when the TFT channel is formed and another one time in Step 5 when the pixel electrode is formed. Since the degree of the wet etching is hard to be controlled, over-etch on the TFT channel occurs easily. Over-etch is an considerable defect for the TFT channel that is important for the array substrate and can widen TFT channel and adversely effect the whole characteristics of the final liquid crystal display.